Abanoub E. Abdelmalak

School of Electrical & Computer Engineering

Georgia Institute of Technology

Atlanta, GA 30332

I spent eight years inside an EDA vendor watching which parts of the semiconductor stack actually break in a fab. I am now an ECE PhD Researcher at the Georgia Institute of Technology, advised by Prof. Ali Adibi, working on the same problems from the physics side.

My research direction is hardware-aware machine learning, and I am moving toward quantum error correction as a longer-term target. Both rest on the same conviction: models that respect the physics of the device they run on beat models that treat it as an abstraction.

Before the PhD, I was at Siemens Digital Industries Software from 2017 to 2025, first as an IC Design Consultant based in Shanghai and then as a Principal Product Architect. I built OPC model-building automation and Resolution Enhancement Technique (RET) flows, developed computational models and test masks for technology ramps spanning nodes from 90 nm KrF to 5 nm ArF immersion, and led delivery across China, Europe, and the US, including one engagement with a Chinese fab that began as a one-month scope and became a six-year partnership. In the last stretch I architected LLM tooling for physical verification, which became my first publication.

I hold an MSc in Computer Science (Machine Learning specialization) from Georgia Tech and a BSc in Communication Systems Engineering with an Optics specialization from Ain Shams University, where I ranked first in the Optics track.

Venn diagram of three overlapping fields: machine learning, quantum computing, and semiconductor design. The machine learning and semiconductor overlap is labelled AI for EDA; the machine learning and quantum overlap is labelled ML for quantum error correction; the centre where all three meet is labelled as the PhD objective. — My work sits across three fields. Only one pairwise area is work I have actually built: AI for EDA at Siemens. Machine learning for quantum error correction is the direction I am moving toward, not a record I can point at yet, and the centre where all three meet is the PhD objective.

Selected Work

SVRF Copilot: AST-guided fine-tuning and retrieval-augmented generation for synthesizing physical verification code. Published at IEEE ICLAD 2025, where AST guidance improved code generation accuracy by up to 40% over text-based fine-tuning on a 741-example DRC benchmark.
OPC and Inverse Lithography: GPU-accelerated inverse lithography and model-based OPC for sub-14 nm nodes, formulated so that edge placement, process window, and mask manufacturability are optimized together rather than traded silently.
ML TCAD Process Modeling: Fourier Neural Operator surrogates for etch and deposition simulation, built to make process-window exploration interactive rather than overnight.

The full set is on the projects page, and my CV has the complete record.

Publication

2025

ICLAD
An AST-guided LLM Approach for SVRF Code Synthesis

Abanoub E. Abdelmalak, Mohamed A. Elsayed, Ilhami Torunoglu, and 1 more author

In Proceedings of the 1st IEEE International Conference on LLM-Aided Design (ICLAD), Jun 2025

Abs arXiv Bib HTML

Standard Verification Rule Format (SVRF) is essential for semiconductor applications like Design Rule Check (DRC), Layout Versus Schematic (LVS), and Optical Proximity Correction (OPC) and it faces challenges as advancing nodes create complex design rules that renders traditional SVRF development ineffective and highlight an expertise gap. This paper introduces a novel methodology integrating Abstract Syntax Tree (AST) embedding and Retrieval-Augmented Generation (RAG) for enhanced SVRF code synthesis, ensuring semantic accuracy and error minimization through structural validation with domain-specific insights for precise code generation. We evaluate different T5-based models and propose an innovative SVRF-specific scoring framework that complements standard metrics like BLEU and ROUGE-L. In our approach, AST provides rigorous structural validation, while RAG infuses relevant domain knowledge, effectively enhancing the code generation workflow. Testing on a comprehensive benchmark of 740 DRC rule implementations, our methodology demonstrates up to a 40 percent improvement in code generation accuracy compared to basic text-based fine-tuning process. This fusion of industry expertise with advanced coding strategies not only optimizes SVRF development under limited dataset constraints but also creates a more intuitive and efficient coding environment. Consequently, users can rapidly iterate through design cycles, reduce manual error correction, and significantly improve overall productivity.
@inproceedings{abdelmalak2025ast, title = {An AST-guided LLM Approach for SVRF Code Synthesis}, author = {Abdelmalak, Abanoub E. and Elsayed, Mohamed A. and Torunoglu, Ilhami and Abercrombie, David}, booktitle = {Proceedings of the 1st IEEE International Conference on LLM-Aided Design (ICLAD)}, year = {2025}, month = jun, pages = {68--76}, }

Contact Me

If you would like to discuss research, collaborations, or consulting opportunities, please feel free to reach out.

Email abanoub_abdelmalak@gatech.edu

LinkedIn abanoub-wahib

Google Scholar Publications

GitHub AbanoubElkess

Office School of ECE, Georgia Tech

News

Aug 18, 2025	Started my PhD in Electrical & Computer Engineering at Georgia Tech, advised by Prof. Ali Adibi.
Jun 26, 2025	Presented An AST-guided LLM Approach for SVRF Code Synthesis at the inaugural IEEE International Conference on LLM-Aided Design (ICLAD 2025), Stanford University.
Dec 14, 2024	Completed my MSc in Computer Science (Machine Learning specialization) at Georgia Tech.